Engineering Root Cause & System Profile
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Selected Sample
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Burn-In
0–45 min · 5.97M → 5.60M/s
Two effects overlap here, not one: ASan/UBSan shadow-memory instrumentation is a constant throughput tax present for the entire run (this is why the whole soak sits at 5.2–5.9M/s rather than the ~7.28M/s clean-build sustained figure — see side note below) — and separately, the CPU package is still settling out of its initial clock/turbo state in this window, which is what actually produces the visible decline.
Thermal Gate
45–60 min · p99.99 steps 134ms → 268ms
Consistent with the laptop chassis settling onto its sustained (PL1) power limit rather than a code-level regression — correctness and heap-allocation counters are flat across this exact window, which is what distinguishes a thermal/frequency effect from an actual defect. Not independently confirmed with a core-temperature sensor during this specific run; inferred from the shape of the curve, stated as such rather than as a directly measured fact.
Steady-State Plateau
60–159 min · 5.16M–5.33M/s floor
Ten samples averaged across the remaining ~100 minutes hold inside a 5.16M–5.33M/s band with zero further drift, zero heap allocations on every single sample, and a produced/consumed deficit that keeps shrinking as a percentage over time (0.0059% → 0.0022%). That combination — flat throughput, flat correctness, shrinking backlog — is what rules out both a ring-buffer leak and consumer drain starvation as concerns.
Core topology. Intel i7-14650HX, hybrid 8P+8E (16 physical cores / 24 logical threads). This soak's 16 pinned threads (8 producers + 8 consumers) occupy logical cores 0–15 — the 8 P-cores via Hyper-Threading — exclusively; logical cores 16–23 (the 8 E-cores) are never touched by this workload. Verified directly, not assumed: isolating each of the 24 logical cores individually with a pinned busy-loop probe measured 4,340–4,577 Miters/sec on cores 0–15 versus 1,944–2,073 Miters/sec on cores 16–23 — a clean, non-overlapping split.
Cache-line isolation. alignas(64) on enqueue_pos_/dequeue_pos_ keeps the producer and consumer cursors on separate cache lines. Measured directly via a false-sharing A/B (two atomic counters, 20M increments each, shared line vs. alignas(64)-separated): 1.29x–1.41x speedup across repeated runs on this machine. Zero false sharing between the two hot cursors is a structural property of the type (static_assert-enforced), not just an observed correlation.